Dual arbiters for arbitrating access to a first and second bus i

Details Dual arbiters for arbitrating access to a first and second bus i Dual arbiters for arbitrating access to a first and second bus i

1997-11-19

1999-07-13

Sheikh, Ayaz R.

395294, 395299, 395728, 395726, G06F 1300

Patent

active

059238593

ABSTRACT:
Arbitration circuitry in a computer system having a plurality of arbiters for arbitrating requests from bus masters on a PCI bus and an EISA bus. Each of the PCI and EISA buses have a plurality of masters. The PCI bus utilizes a modified LRU arbitration scheme, while the EISA bus utilizes a rotating priority scheme. The arbiter on the EISA bus includes a first level of arbitration and a second level of arbitration. The first level is assigned a plurality of requester types to determine the priority between the requestor types. Certain of the first level requestor types include a plurality of devices. If one of those certain requestor types wins priority on the first level arbitration cycle, a second level arbitration is performed to determine the priority between the plurality of devices.

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