Semiconductor electrically erasable and writeable non-volatile m

Details Semiconductor electrically erasable and writeable non-volatile m Semiconductor electrically erasable and writeable non-volatile m

1997-02-18

1999-07-13

Nguyen, Hoa T.

Excavating

371 212, G11C 2900

Patent

active

059236744

ABSTRACT:
In a semiconductor electrically erasable and writable non-volatile memory device, a memory cell array 14 includes a test memory region 142 for a writing test, and there are provided a writing test circuit for generating a writing test signal WTEST, a write voltage-detecting circuit 18 for generating a voltage-detecting signal WREN when a writing voltage supplied to the region 142 is less than a reference value at the time of writing test, and an output buffer circuit 15 which switches it to a test output mode in response to the supply of the writing test signal WTEST and outputs a write inhibit information in response to the supply of voltage-detecting signal WREN.

REFERENCES:
patent: 5287317 (1994-02-01), Kobayashi et al.
patent: 5428574 (1995-06-01), Kuo et al.
patent: 5475646 (1995-12-01), Ogihara
patent: 5687178 (1997-11-01), Herr et al.

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