Method for eletronically representing a number, adder circuit an

Details Method for eletronically representing a number, adder circuit an Method for eletronically representing a number, adder circuit an

1997-08-15

1999-07-13

Kizou, Hassan

Boots, shoes, and leggings

36474807, 36474811, G06F 738

Patent

active

059235756

ABSTRACT:
The invention relates to a method for electronically representing a number V in a binary data word. Both the exponent and the mantissa are represented as 2' complement. The mantissa is normalized to 0.1.F if the number V is positive where F is the fraction of the mantissa. In case that the number V is negative the fraction F is normalized to 10.F. Usage of this format allows to design an improved adder which requires less hardware.

REFERENCES:
patent: 4841467 (1989-06-01), Ho et al.
patent: 5257215 (1993-10-01), Poon
patent: 5570309 (1996-10-01), Miyoshi et al.
patent: 5574672 (1996-11-01), Briggs

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