Patent
1995-12-19
1999-04-13
Sheikh, Ayaz R.
38740, 38741, 38742, G06F 946
Patent
active
058945784
ABSTRACT:
A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central interrupt controller, random access memory, and at least one processor interface. The central interrupt controller systematically selects interrupt requests from the interrupt request interface. Information associated with each interrupt request is stored in the random access memory. The central interrupt controller access the information in the random access memory and uses the information and the state of the currently selected interrupt request to determine a next state for the currently selected interrupt request. The information is passed on to the processor interface to determine when and if the interrupt request should issue to one of the CPUs.
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Intel MultiProcessor Specification Version 1.1, Apr. 1994, pp. 1-54.
Bailey Joseph A.
Mudgett Dan S.
Qureshi Qadeer A.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Pancholi Jigar
Sheikh Ayaz R.
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