Methods and apparatus for maximizing column address coherency fo

Details Methods and apparatus for maximizing column address coherency fo Methods and apparatus for maximizing column address coherency fo

1990-03-16

1993-08-03

Harkcom, Gary V.

395164, G06F 1562

Patent

active

052336891

ABSTRACT:
Methods and apparatus for maximizing column address coherency for serial and parallel port accesses to a dual port frame buffer. Performance of the serial port of the frame buffer is greatly improved by separating the page boundaries in the horizontal direction (i.e., scan line organized), while performance of the parallel port of the frame buffer is enhanced by organizing the page boundaries for rectangular areas of the display. Performance at both ports may be maximized at the same time by organizing the video random access memory (VRAM) into tiles and vertically barrel shifting the scan line data at a fixed interval across the video display. During operation, the serial port output looks like an entire row of data while it has actually output parts of N rows of data from two separate rows of memory chips which are changed at the fixed interval. This approach allows the parallel port to organize columns N times higher in the vertical direction. As a result, the page boundaries are N times as far apart in the vertical direction, thereby improving output performance.

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