Excavating
Patent
1990-08-29
1993-08-03
Beausoliel, Jr., Robert W.
Excavating
371 52, 371 211, 371 401, 365200, 365201, G06F 1100
Patent
active
052336107
ABSTRACT:
A semiconductor memory device comprises a memory array, a test mode detecting circuit, an address counter, a correction circuit, and a data counter. When a test mode enable signal is applied externally to the test mode detecting circuit, the address counter sequentially addresses the memory array. The correction circuit detects the error of the data sequentially read out from the memory array. The data counter counts the number of data to be corrected by said correction circuit. The counting result is outputted to the exterior.
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Hayashikoshi Masanori
Kobayashi Kazuo
Miyawaki Yoshikazu
Nakayama Takeshi
Terada Yasushi
Beausoliel, Jr. Robert W.
Hua Ly V.
Mitsubishi Denki & Kabushiki Kaisha
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