Method for assuring fidelity of a summing process

Details Method for assuring fidelity of a summing process Method for assuring fidelity of a summing process

1991-10-03

1993-08-03

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 77, H04L 1218, H04Q 1104

Patent

active

052336050

ABSTRACT:
In a digital summing process that sums non-linear digital signals by converting them to linear signals, computing their two's complement, summing the two's complements together and converting the resultant into a non-linear resultant, the fidelity of the summing process may be verified in the following manner. When only one non-linear digital signal is being summed, an algorithm determines whether the one non-linear digital signal being summed is equivalent to a predetermined value which, when passed through the summing process, will yield a different value than the one inputted. If the algorithm determines that the one non-linear digital signal is equivalent to a predetermined value, it sets a flag which indicates that the resultant over written with the predetermined value. Once the resultant is overwritten with the predetermined value, the flag is reset.

REFERENCES:
patent: 3924082 (1975-12-01), Oliver et al.
patent: 4658398 (1987-04-01), Hsing
patent: 4797876 (1989-01-01), Ratcliff
patent: 5054021 (1991-10-01), Epps

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