Time interval triggering and hardware histogram generation

Details Time interval triggering and hardware histogram generation Time interval triggering and hardware histogram generation

1992-11-16

1993-08-03

Cosimano, Edward R.

Boots, shoes, and leggings

377 13, G06M 308

Patent

active

052335453

ABSTRACT:
A time interval data processing circuit uses a pipelined hardware data processor to perform the conversion of incoming time stamp data into time interval results. These results can be further processed into a hardware accumulated histogram or can be compared against limits to determine if a time interval trigger condition has occurred. In the first stage of the pipeline, the processing circuit subtracts the two time stamps from the current and the previous event to determine the time interval between events being measured. The second stage checks the measurement result against minimum and maximum limits and determines which bin the measurement belongs in. The limit testing determines if the measurement fits the histogram limits and also yields the data required to perform measurement triggering on time intervals. The third stage of the pipeline increments the appropriate histogram bin in RAM. The first and third stages of the pipeline are themselves pipelined in substages. To facilitate pipelining in storing the histogram results, the circuit uses dual port RAMs to achieve a fast data accumulation rate. When histogramming, the stored bin data must be incremented each time a new measurement occurs. The third pipeline stage read, increment, write operation is pipelined in substages by adding a latch in the data incrementing loop for the dual port RAM. The latch also provides a way of avoiding access conflicts when the same bin is incremented repeatedly.

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Hewlett-Packard Journal, Feb., 1989, p. 35-41.
M. Abdelguerfi, et al.--"Parallel Bit-Level Pipelined VLSI Processing Unit for the Histogramming Operation"--Jun. 1988--pp. 945-950.

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