Method of reducing chip size by modifying main wordline repair s

Details Method of reducing chip size by modifying main wordline repair s Method of reducing chip size by modifying main wordline repair s

1996-06-13

1998-04-07

Beausoliel, Jr., Robert W.

G06F 1118, G06F 1120

Patent

active

057375119

ABSTRACT:
A method and apparatus for effecting repair or replacement of defective circuits in a solid state memory chip that includes the use of logic circuits to replace the fuse circuits. Included in the method and apparatus for effecting repair of defective circuits is a circuit for switching redundancy spare cells in place of main wordline cells. A logic circuit is used in order to reduce the chip size by getting rid of a fuse in the X-decoder. When a redundancy circuit is used, the logic circuit automatically generates a RM signal to control the X7 predecoder to turn off the main wordline. Included in an apparatus for effecting replacement of main circuits in a solid state memory chip are a first inverter for receiving a first signal indicating whether a predetermined circuit is selected, a second inverter connected to the output of first inverter for providing an inverted output of the output of the first inverter, a third inverter connected to the output of the second inverter for providing an inverted output of the output of the second inverter, a first circuit for receiving a first fixed input and a second varying input having a first enabling state and a second disabling state and providing an output having an enabling state and a disabling state and a second circuit for receiving a first input from the output of the third inverter and a second input from the output of the first circuit and providing an enabling output whenever the main circuit is selected and a disabling output whenever the main circuit is to be replaced.

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M. Morris Mano, Digital Design 2nd ed., 1991, pp. 72-78, 88-98, Prentice-Hall, Inc.

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