Mechanism for enabling multi-bit counter values to reliably cros

Details Mechanism for enabling multi-bit counter values to reliably cros Mechanism for enabling multi-bit counter values to reliably cros

1995-09-29

1999-04-13

Butler, Dennis M.

395558, 395309, G06F 104

Patent

active

058945679

ABSTRACT:
A queue structure for transmitting a multiple-bit signal from a first sub-system operating in a first clocking domain in a computer system to a second sub-system operating in a second clocking domain in the computer system is disclosed. The queue structure comprises a queue data latch having a plurality of storage elements, wherein each of the plurality of storage elements can store the multiple-bit signal from the first sub-system. A load pointer is used for generating a first multiple-bit count indicating one of the plurality of storage element for storing the multiple-bit signal. A synchronization unit is coupled to the load pointer for receiving the first multiple-bit count. The synchronization unit outputs the multiple-bit count at the second sub-system when the multiple-bit signal is ready to be sampled in the second clocking domain.

REFERENCES:
patent: 4873703 (1989-10-01), Crandall et al.
patent: 5426756 (1995-06-01), Shyi et al.
patent: 5546546 (1996-08-01), Bell et al.

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