Method for fabrication vertical NPN and PNP structures utilizing

Details Method for fabrication vertical NPN and PNP structures utilizing Method for fabrication vertical NPN and PNP structures utilizing

1977-10-25

1979-07-03

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

29576B, 29576C, 29576W, 148175, 148187, 148190, 148191, 156643, 156648, 156653, 156662, 357 15, 357 44, 357 46, 357 50, 357 91, 357 92, 427 84, H01L 21265, H01L 2174

Patent

active

041599152

ABSTRACT:
A method is given for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon isolated from one another by isolation regions. Buried regions are formed overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach-through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP regions is then implanted by suitable ion implantation techniques. A Schottky Barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.

REFERENCES:
patent: 3611067 (1976-07-01), Oberlin et al.
patent: 3648130 (1972-03-01), Castrucci et al.
patent: 3823353 (1974-07-01), Berger et al.
patent: 3861968 (1975-01-01), Magdo et al.
patent: 3901735 (1975-08-01), Dunkley
patent: 3922565 (1975-11-01), Berger et al.
patent: 3924264 (1975-12-01), Dorler et al.
patent: 3930909 (1976-01-01), Schmitz et al.
patent: 3968272 (1976-07-01), Anand
patent: 3999080 (1976-12-01), Weathersby, Jr. et al.
patent: 4005469 (1977-01-01), Chang et al.
patent: 4021270 (1977-05-01), Hunt et al.
patent: 4032962 (1977-06-01), Balyoz et al.
patent: 4035664 (1977-07-01), Berger et al.
patent: 4075039 (1978-02-01), Sloan
patent: 4076556 (1978-02-01), Agraz-Guerena et al.
patent: 4087900 (1978-05-01), Yiannoulos
patent: 4106049 (1978-08-01), Shinozaki et al.
Fogiel, Max, "Modern Microelectronics" published by Research and Education Assoc., New York, N.Y. 10017, 1972, pp. 463-472.
Daughton, J. M., "Vertical Schottky Pad", I.B.M. Tech. Discl. Bull., vol. 15, No. 1, Jun. 1972, p. 261.
Abbas et al., "Complementary Bipolar Transistor . . . Steps"
Ibid., vol. 16, No. 5 Oct. 1973, pp. 1630-1631.
Jacobus et al., "Complementary Transistors" I.B.M. Tech. Discl. Bull., vol. 14, No. 4, Sep. 1971, p. 1045.
Stone, J. L., "I.sup.2 L: A Comprehensive Review . . . Technology" Solid State Technology, Jun. 1977, pp. 42-48.

Affiliated with

Also associated with

Rating

Method for fabrication vertical NPN and PNP structures utilizing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabrication vertical NPN and PNP structures utilizing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabrication vertical NPN and PNP structures utilizing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2274009