Method and apparatus for controlling bus arbitration in a data p

Details Method and apparatus for controlling bus arbitration in a data p Method and apparatus for controlling bus arbitration in a data p

1996-10-28

1999-04-13

Sheikh, Ayaz R.

395288, 395856, 395726, 395729, 395728, G06F 1336

Patent

active

058945628

ABSTRACT:
A method of controlling bus arbitration using an arbitration bit to lock ownership of the bus and prevent bus grants pending completion of a predetermined sequence. In a data processing system (15) having multiple potential bus masters, competing bus ownership requests are resolved by an arbiter (9) resident on one of the bus masters (11). In one embodiment, for execution of a sequence of inseparable cycle data accesses, a central processing unit (3) causes an arbitration bit (22) in a control register (20) to be set. Once the arbitration bit (22) is set, the arbiter will effectively lock the bus, and will not provide a bus grant signal until the arbitration bit (22) is cleared. A timer (7) counts to a predetermined value, where upon completion the arbitration bit is cleared allowing arbiter (9) to provide bus grant signals. The present invention allows locking of bus arbitration during a pending inseparable sequence of data accesses without the use of special instructions or external signals.

REFERENCES:
patent: 5068781 (1991-11-01), Gillett et al.
patent: 5430848 (1995-07-01), Waggener
patent: 5710891 (1998-01-01), Normoyle et al.
Motorola Inc. Apr. 1985 Semiconductors Advance Info., "MC68008 8-/32-Bit Microprocessor with 8-Bit Data Bus", pp. 4-10 -4-21.
Motorola Inc., pub. by Prentice Hall, Englewood Cliffs, N.J., "MC68020 32-Bit Microprocessor User's Manual", Third Edition, pp. 7-40 -7-45.
Motorola Inc. 1990, DSP56116 User's Manual, "DSP56116 Digital Signal Processor User's Manual", pp. 8-2 -9-3.

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