Boots – shoes – and leggings
Patent
1987-08-11
1988-10-25
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 1300, G11C 700
Patent
active
047808071
ABSTRACT:
This pipeline processor has an ALU, an accumulator register, a first data bus connected through a first switch circuit to output terminals of the accumulator register, and a second data bus connected to input terminals of the accumulator register through a second switch circuit. Data on the first data base is processed by the ALU, and supplied through a third switch circuit to the second data bus. First to third switch circuits respectively receive first to third control signals generated at a predetermined timing for controlling the data transfer by the signal generator of an execution control circuit. The execution control circuit is further provided with signal generator for generating a fourth control signal which renders the second switch circuit conductive during the precharge period of the first and second data buses. The third and fourth control signals are supplied through an OR gate to the second switch circuit.
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IBM Technical Bulletin, vol. 14, No. 10, Mar. 1972, "Parallel Pipeline Organization of Execution Unit".
Anderson Lawrence E.
Harkcom Gary V.
Kabushiki Kaisha Toshiba
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