Patent
1986-02-18
1988-10-25
Clawson, Jr., Joseph E.
357 237, 357 41, 357 51, 357 59, H01L 2978
Patent
active
047807512
ABSTRACT:
A semiconductor integrated circuit device having a flip-flop circuit with first and second insulated gate field effect transistors is disclosed. The gate electrode of the first transistor is connected to one impurity region of source and drain regions of the second transistor, and the gate electrode of the second transistor is connected to one impurity region of source and drain regions of the first transistor. A part of the one impurity region of the first transistor and a part of the one impurity region of the second transistor are overlapped each other with an insulating film being interposed therebetween to form a capacitor element by using the impurity regions as upper and lower electrodes, respectively, and the insulating film as a dielectric film.
REFERENCES:
patent: 4488348 (1984-12-01), Jolly
patent: 4541006 (1985-09-01), Ariizumi et al.
patent: 4570175 (1986-02-01), Miyao et al.
patent: 4656731 (1987-04-01), Lam et al.
R. Garnache, "Complementary FET Memory Cells, " IBM Tech. Discl., Bull., vol., 18 #12, May 1976, pp. 3947-3948.
Clawson Jr. Joseph E.
NEC Corporation
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