Process for fabricating high voltage CMOS with self-aligned guar

Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

29571, 148 15, 357 23, 357 42, 357 50, 357 52, H01L 2122, H01L 2978

Patent

active

041359550

ABSTRACT:
Complementary MOS devices having spaced guard rings are fabricated by applying an oxide layer to an N substrate with an opening for doping P-type impurities to form a well, applying a nitride layer over a portion of the oxide and of the well portions, doping the area in the well between the nitride and the oxide to form P-type guard rings, masking the well and adjacent portion of the oxide, doping the area between the mask and the exposed nitride layer to form N-type guard rings and exposing the substrate to an oxidizing atmosphere to oxidize the substrate except where covered by the nitride layer. The nitride layer is removed and standard device processing is used to form complementary MOS in the areas previously covered by the nitride.
The resulting integrated circuit includes a P-type guard ring extending laterally from the outer edge of the N-channel source and drain to the edge of the P-type well and a N-type guard ring extending laterally from the outer edge of the P-channel device source and drain to a point adjacent, but spaced from the P-type well. The inner lateral edges of the guard rings are laterally aligned with the outer edges of the source and drains and the top surface of the guard rings are vertically displaced from the top surface of the source and drains by the oxide formed in the substrate.

REFERENCES:
patent: 3673428 (1972-06-01), Athanas
patent: 3853633 (1974-12-01), Armstrong
patent: 3983620 (1976-10-01), Spadea
patent: 4006491 (1977-02-01), Alaspa et al.
patent: 4013484 (1977-03-01), Buleky et al.
patent: 4027380 (1977-06-01), Deal et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for fabricating high voltage CMOS with self-aligned guar does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating high voltage CMOS with self-aligned guar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating high voltage CMOS with self-aligned guar will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2271683

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.