Domino-type MOS logic gate having an MOS sub-network

Details Domino-type MOS logic gate having an MOS sub-network Domino-type MOS logic gate having an MOS sub-network

1987-03-26

1988-10-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307453, H03K 19096, H03K 19003

Patent

active

047806265

ABSTRACT:
The invention relates to a logic MOS gate of the domino type, having a precharging transistor, a validation transistor and logic transistors. To prevent unwanted discharging of a precharged high level, which may be induced by at least one input data being stabilized too slowly, that is to say not before a clock signal has risen to the high level, a p-MOS sub-network is arranged in parallel with the source-drain path of the precharging transistor and receives at least the input data which was too slowly stabilized in such a manner as to establish a conductor path which reestablishes the precharged high level.

REFERENCES:
patent: 3517210 (1970-06-01), Rubinstein
patent: 3573487 (1971-04-01), Polkinghorn
patent: 3953743 (1976-04-01), Hollingsworth
patent: 3982138 (1976-09-01), Luisi et al.
patent: 4107548 (1978-08-01), Sakaba et al.
patent: 4430583 (1984-02-01), Shoji
patent: 4558236 (1985-12-01), Burrows

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