Dynamic MOS memory with reduced propagation delay

Details Dynamic MOS memory with reduced propagation delay Dynamic MOS memory with reduced propagation delay

1976-03-10

1977-04-05

Fears, Terrell W.

Communications: electrical

Digital comparator systems

307238, 307279, G11C 1140

Patent

active

040165515

ABSTRACT:
The present invention relates to an improved MOS memory structure. There is disclosed an array of memory cells of the three-device-per-bit type, the array being formed in rows and columns. Temporary storage cells are disclosed which are employed to receive and temporarily store inverted digital information from selected memory cells responsive to a READ signal. The inverted digital information is re-inverted upon restoration thereof into the selected memory cells, thus eliminating any need of accounting for the polarity or status of the data, whereby propagation delay time through the memory structure is reduced.

REFERENCES:
patent: 3986173 (1976-10-01), Baitinger

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