Process for fabricating electrically alterable floating gate mem

Details Process for fabricating electrically alterable floating gate mem Process for fabricating electrically alterable floating gate mem

1987-09-28

1988-10-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 30, 437 43, 357 235, 357 2311, H01L 21425, H01L 2978

Patent

active

047804246

ABSTRACT:
A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The contactless cells use elongated source and drain regions disposed beneath field oxide regions. The drain regions are shallow compared to the source regions. The source regions have more graded junctions. Floating gates are formed over a tunnel oxide (120 .ANG. thick) between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gates is formed after the word lines have been patterned by etching the first layer of polysilicon in alignment with the word lines.

REFERENCES:
patent: 4214359 (1980-07-01), Kahng
patent: 4258466 (1981-03-01), Kuo et al.
patent: 4435895 (1984-03-01), Parrillo et al.
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4561004 (1985-12-01), Kuo et al.

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