Longitudinal parity generator for use with a memory

Details Longitudinal parity generator for use with a memory Longitudinal parity generator for use with a memory

1976-03-01

1977-04-05

Atkinson, Charles E.

Registers

Transfer mechanism

Traveling pawl

3401461AG, G06F 1110, G11C 2900

Patent

active

040164098

ABSTRACT:
Longitudinal parity is continuously provided for a predetermined plurality of words stored in a digital memory in a simple and expeditious manner without interfering with normal memory operation. The outputs of the memory read and write registers are applied in corresponding bit pairs to respective ones of a plurality of Exclusive ORs whose outputs are employed to update the respective flip flops of a longitudinal parity register at a time which is specially chosen so that the old word read out of the memory and the new word to be written therein are simultaneously available in the read and write registers.

REFERENCES:
patent: 3805040 (1974-04-01), Boden et al.
patent: 3876978 (1975-04-01), Bossen et al.
patent: 3887901 (1975-06-01), Moore

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