Patent
1978-06-05
1981-02-17
Wojciechowicz, Edward J.
357 52, 357 53, 357 55, 357 56, 357 59, H01L 2978
Patent
active
042518288
ABSTRACT:
An improvement for preventing a short circuit between the source and drain regions of an MOS type semiconductor device. The source and drain regions are placed on an insulating layer to reduce the junction capacitance between these layers and a semiconductor substrate in the MOS type semiconductor device. The polycrystalline silicon, which was present in the conventional device between the source and drain regions, and thus caused the short, is changed by the improvement to an insulating material. Disclosed also herein is an advantageous process for producing the semiconductor device.
REFERENCES:
patent: 4041518 (1977-09-01), Shimizu et al.
I.E.D.M. Tech. Digest (1973)-pp. 244-247.
Fujitsu Limited
Wojciechowicz Edward J.
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