Semiconductor memory with divided bit load and data bus lines

Details Semiconductor memory with divided bit load and data bus lines Semiconductor memory with divided bit load and data bus lines

1988-02-19

1990-06-19

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Plural blocks or banks

365190, 36518902, 365 63, 365227, G11C 800

Patent

active

049359010

ABSTRACT:
A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

REFERENCES:
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patent: 4802132 (1989-01-01), Ohsawa
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CMOS Memory: A 65Kb Full CMOS RAM with Divided Word Line Structure by Masahiko Yoshimoto, et al. ISSCC Digest of Technical Papers, Feb. 1983, pp. 58-59.
A 20 ns 64K CMOS Static RAM by Minato, et al. IEEE Journal of Solid State Circuits, vol. SC-19, No. 6, Dec. 1984, pp. 1008-1013.

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