Data transfer control method, and peripheral circuit, data proce

Details Data transfer control method, and peripheral circuit, data proce Data transfer control method, and peripheral circuit, data proce

1995-01-06

1997-09-30

Harvey, Jack B.

395881, 395550, G06F 1336

Patent

active

056733984

ABSTRACT:
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

REFERENCES:
patent: 4755937 (1988-07-01), Glier
patent: 5140680 (1992-08-01), Best
patent: 5268865 (1993-12-01), Takasugi
patent: 5309567 (1994-05-01), Mizukami
patent: 5371880 (1994-12-01), Bhattacharya
patent: 5446696 (1995-08-01), Ware et al.
patent: 5457781 (1995-10-01), Millar et al.
patent: 5469549 (1995-11-01), Simpson et al.
patent: 5469577 (1995-11-01), Eng et al.
patent: 5537640 (1996-07-01), Pawlowski et al.

Affiliated with

Also associated with

Rating

Data transfer control method, and peripheral circuit, data proce does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data transfer control method, and peripheral circuit, data proce, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data transfer control method, and peripheral circuit, data proce will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2263612