Method of monitoring a computer simulation of an electrical circ

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

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716 6, G06F 1750

Patent

active

061310808

ABSTRACT:
A simulation monitor (502) automatically generates a monitor file (510) from a static timer output file (504). The monitor file instantiates a function, a firing equation, that triggers if and only if a critical timing path also triggers. The monitor file is written in a high level language description, suitable for efficient simulation. The test vectors which trigger the firing equation can thereby be monitored and used for hardware test at a later time. The invention may be extended to monitor other conditions of interest.

REFERENCES:
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patent: 5675728 (1997-10-01), Kunda et al.
patent: 5812416 (1998-09-01), Gupte et al.
patent: 5943498 (1999-08-01), Yano et al.
Palnitkar et al.: Finite state machine trace analysis program; IEEE Veilog HDL Conf.; pp. 52-57, 1994.

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