1991-02-21
1992-03-31
Wojciechowicz, Edward J.
357 238, 357 41, 357 46, 357 54, 357 55, H01L 2968
Patent
active
051012480
ABSTRACT:
An electrically erasable and programmable non-volatile semiconductor having a selection transistor, a memory transistor, and a logic transistor. The selection transistor has a first gate insulating film of a first film thickness and is made operative by a gate voltage of about 20V. The memory transistor has a second gate insulating film comprising a first portion whose film thickness is the same as the first film thickness and a second portion of a second film thickness smaller than the first film thickness. The memory transistor also has an electrically floating gate arranged on the second gate insulating film. The logic transistor has a third gate insulating film of a third film thickness smaller than the first film thickness but larger than the second film thickness and is made operative by a gate voltage of about 5V. When the second film thickness is represented by A, the third film thickness by B, and the first film thickness by C, A:B:C=1:2.1:4.2.
REFERENCES:
patent: 4988635 (1991-01-01), Ajika et al.
patent: 5008721 (1991-04-01), Gill et al.
Kabushiki Kaisha Toshiba
Wojciechowicz Edward J.
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