Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Patent
1996-08-26
1997-09-30
Chin, Stephen
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
370512, H04L 700
Patent
active
056732961
ABSTRACT:
A frame synchronization circuit which detects a frame synchronization bit allotted in a particular position within a receiving data string includes a shift register, a synchronization pattern detection circuit and a control circuit. The shift register receives and stores the receiving data string and outputs a parallel data string. The synchronization pattern detection circuit receives the parallel data string outputted from the shift register in synchronization with a clock signal and makes decisions simultaneously on the matching
on-matching of a parallel data string of totally r bits disposed in an n bit cycle within the receiving data string with r kinds of predetermined synchronization patterns of r bits. The control circuit receives an output of the synchronization pattern detection circuit, and outputs either a signal indicative of the in-synchronization state through a terminal or a signal indicative of the out-of-synchronization state through a terminal. This enhances the synchronization reset characteristics and reduces the worst average synchronization reset time.
REFERENCES:
IEEE Transactions on Communications, vol. 33, No. 5, 1 May 1985, pp. 465-469, David E. Dodds, "Robust frame synchronisation for noisy pcm systems".
Chin Stephen
NEC Corporation
Phan Hai H.
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