Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Patent
1990-06-29
1992-03-31
Pellinen, A. D.
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
377 80, H03M 900
Patent
active
051012030
ABSTRACT:
A substantially simultaneous digital data regeneration and deserialization technique for communication systems and information and data processing systems is disclosed. A digital phase lock logic circuit (DPLL) receives the serial stream of clock and data bits at its input and outputs a plurality of clock signals with different phase. A plurality of latches are coupled to receive a respective one of the clock output signals from the DPLL. Each latch receives the serial stream of clock and data bits through a second input such that the latches are sequentially set by substantially simultaneously received clock and data information at the two inputs and the serial data bits within the stream appear as parallel data bits at the latch outputs. Enhanced versions of this circuit are also described, along with an alternate embodiment which uses an analog phase locked loop circuit.
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Gersbach John E.
Novof Ilya I.
International Business Machines - Corporation
Pellinen A. D.
Young Brian K.
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