Semiconductor memory device operating stably under low power sup

Details Semiconductor memory device operating stably under low power sup Semiconductor memory device operating stably under low power sup

1995-06-06

1997-09-30

Nguyen, Viet Q.

Static information storage and retrieval

Powering

365203, 36518907, 36518905, 36518909, H01L 2704

Patent

active

056732325

ABSTRACT:
A semiconductor memory device of the present invention includes an internal power supply voltage generating circuit down converting external power supply voltage to generate first and second internal power supply voltages, a Vpp generating circuit generating a high voltage from external power supply voltage by charge pumping operation, and a Vbb generating circuit generating negative voltage from external power supply voltage by charge pumping operation. The first internal power supply voltage is applied to a control circuit and a sense amplifier drive signal generating circuit. The second internal power supply voltage is applied to a circuit generating a bit line equalize/precharge signal. Even if the first internal power supply voltage is made small, the Vpp generating circuit and the Vbb generating circuit generate a prescribed voltage from external power supply voltage. Therefore, these circuits generate a prescribed internal high voltage and negative voltage efficiently and stably. The bit line equalize/precharge signal is at a voltage level higher than the first internal power supply voltage. The bit line equalize/precharge signal can equalize/precharge a bit line at a high speed. As a result, a semiconductor memory device which operates stably with low power consumption is provided.

REFERENCES:
patent: 5249155 (1993-09-01), Arimoto et al.
"A 1.5V Circuit Technology for 64 Mb DRAMs," by Y. Nakagome et al., Digest for Technical Papers, 1990 Symposium on VLSI Circuits pp. 17-18.

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