Discrete cosine transform processor

Details Discrete cosine transform processor Discrete cosine transform processor

1996-08-28

1997-09-30

Elmore, Reba I.

Boots, shoes, and leggings

382276, 382250, G06F 1714

Patent

active

056732147

ABSTRACT:
Disclosed is an improved discrete cosine transform processor comprising an input unit for receiving image data to be processed, a storage unit for previously storing a result of a multiplication and accumulation calculation effected beforehand with respect to image input data and transform matrix components so that the same value is read from the same read line; a decoding unit for selecting the read line, in which each bit value of the image input data composed of a plurality of bits serves as a piece of address data; an accumulation unit for accumulating the data read from the storage unit and an output unit for outputting a result of the accumulation processing as output data. The storage unit uses the common data in common when effecting the multiplication and accumulation calculation, and, hence, a storage capacity is reduced, thereby making it possible to decrease a chip area.

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Arie Heiman, et al., "A Universal Real-Time Transformer for Image Coding", 1987 IEE Region 10 conference, vol. 2 of 3.
Chan S. Kim, et al., "200 Mega Pixel Rate IDCT Processor for HDTV Applications", 1993 IEEE, vol. 3. May 3-6, 1993.
Shin-ichi Uramoto, et al., "A 100MHz 2-D Discrete Cosine Transform Core Processor", pp. 35-36. No date.
M. Maruyama, et al., "VLSI Architecture and Implementation of a Multi-Function, Forward/Inverse Discrete Cosine Transform Processor", SPIE vol. 1360 Visual communications and Image Processing '90, pp. 410-417.

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