Semiconductor nonvolatile memory apparatus and computer system u

Details Semiconductor nonvolatile memory apparatus and computer system u Semiconductor nonvolatile memory apparatus and computer system u

1999-11-02

2000-10-10

Phan, Trong

Static information storage and retrieval

Floating gate

Particular biasing

36518524, G11C 1606

Patent

active

061308412

ABSTRACT:
After decreasing the threshold voltages of a plurality of memory cells collectively or selectively, the presence or absence of any memory cell of which the threshold voltage has dropped below a predetermined voltage verified collectively for each of memory cell groups connected to word line (low-threshold value verification) , and any memory cell of which the threshold voltage has excessively dropped is selectively written. Also, the well of each of memory cell is formed in the region of an element isolation layer for isolating it from the substrate of a memory apparatus, and a negative voltage is supplied to the memory well distributively with a positive voltage applied as a word line voltage, thus supplying them as erase operation voltages. The absolute value of the memory well voltage is set substantially equal to or lower than the word line voltage for the read operation. Sectors constituting each memory mat includes a sector (selected sector) selected for the erase operation with each word line thereof supplied with a positive voltage, a sector (non-selected sector) not selected for the erase operation with a word line voltage different from a memory well voltage, and further a sector (completely non-selected sector) not selected for the erase operation with a word line voltage equal to the voltage between a source and a drain of the memory cell.

REFERENCES:
patent: 5475249 (1995-12-01), Watsuji et al.
patent: 5886927 (1995-12-01), Takeuchi
Tanaka et al., "High-Speed Programming and Program Verify Methods . . . ", 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 61-62.
Hisamune et al., "A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories" IEEE Meeting Technical Digest 1993.

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