Fishing – trapping – and vermin destroying
Patent
1988-08-03
1990-06-19
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 40, 437 43, 437 49, 437193, 437200, 437982, H01L 2100
Patent
active
049353802
ABSTRACT:
A polyside gate of a prescribed shape with a protection film formed on the upper surface thereof is formed on a main surface of a semiconductor substrate. The protection film protects the upper surface of the polyside gate from oxidation in heat treatment. Impurities are implanted in the semiconductor substrate using the polyside gate and the protection film as a mask. The implanted impurities are diffused in the semiconductor substrate by the heat treatment, thereby providing a MOS transistor. A polyside gate of a prescribed shape is formed on a main surface of a semiconductor substrate and an interlayer insulating film is formed to cover the polyside gate. A protection film is formed on the interlayer insulating film and a reflow film is further formed thereon. The protection film protects the polyside gate from oxidation. The surface of the reflow film is made smooth by the heat treatment.
REFERENCES:
patent: 4332207 (1986-07-01), Levinstein et al.
patent: 4782037 (1988-11-01), Tomozawa et al.
B. Crowder and S. Zirinsky, "1 um MOSFET VLSI Technology: Part VII-Metal Silicide Interconnection Technology-A Future Perspective" IEEE Transactions on Electron Devices, vol. ED-26, No. 4 (Apr. 1979): 369, 371.
P. Tsang et al., "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Transactions on Electron Devices, vol. ED-29, No. 4 (Apr. 1982): 590, 596.
Hearn Brian E.
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tuan
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