Patent
1996-05-06
1998-03-03
Dung, Dinh C.
39542108, 395280, 395464, G06F 1200, G06F 1300
Patent
active
057246130
ABSTRACT:
The present invention relates to a system and method which has automatic enabling and disabling capabilities for prefetching and transferring sequentially located data from system memory to a First In First Out (FIFO) queue. When a Peripheral Component Interconnect (PCI) initiator signals for a data read, a minimum unit of data will be transferred from system memory to the FIFO queue. Only after seeing a certain number of consecutive data read requests from the same PCI initiator will the system begin to sequentially prefetch data from system memory and to transfer the prefetched data to the FIFO queue.
REFERENCES:
patent: 4371924 (1983-02-01), Schaefer et al.
patent: 4807110 (1989-02-01), Pomerene et al.
patent: 4853846 (1989-08-01), Johnson et al.
patent: 4918587 (1990-04-01), Pechter et al.
patent: 5557750 (1996-09-01), Moore et al.
patent: 5566324 (1996-10-01), Kass
patent: 5630094 (1997-05-01), Hayek et al.
Dahlgren et al. "Sequential Hardware Prefetching in Shared Memory Multiprocessors", IEEE Transaction on Parallel Processing Systems, v6 iss7, Jul. 1995.
Zucker et al. "A comparison of Hardware Prefetching Techniques for Multimedia Benchmarks", Multimedia Computing and Systems, 1996 int'l conf., 1996.
Dung Dinh C.
Moy Jeffrey D.
VLSI Technology Inc.
Weiss Harry M.
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