Selector bank subsystem of CDMA system using a pair of first pro

Details Selector bank subsystem of CDMA system using a pair of first pro Selector bank subsystem of CDMA system using a pair of first pro

1995-06-07

1998-03-03

Lee, Thomas C.

Multiplex communications

Wide area network

Packet switching

395858, 370320, 370431, 370441, G06F 1300

Patent

active

057246106

ABSTRACT:
A selector bank subsystem (SBS) of a code division multiple access (CDMA) system is disclosed, including two portions: a SBSC block and a S/V block. The one SBSC block is designed to manage twelve S/V boards so as to provide 96 traffic channels per SBS self, and thus, one S/V board provides eight communication channels. A selector bank subsystem (SBS) of a code division multiple access (CDMA) system, includes: an SBS block, the SBS block being composed of a pair of first processors for controlling the traffic frame communication with a CDMA interconnect subsystem (CIS) by selecting a channel between the CIS and a mobile service switch center (MSC); a dual port RAM (DRAM) for storing the traffic frame by the control of the first processor and being access-controlled by direct memory access controller (DMAC); a second processor for controlling the DMAC; an E1 interface portion for interfacing the frame data with the MSC by receiving synchronism from the TFU of the CPS receiver; and a S/V block being linked between the DRAM and the E1 interface as a plurality of extensible card forms, and for receiving the traffic frame to the E1 interface portion after DSP-processing. Therefore, the subsystem completes the SBS constitution of a mass-production module having competitiveness, avoids a complicated hardware constitution and reduces the possibility of a signal conflict between boards.

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