Method of manufacturing a semiconductor memory using dummy sourc

Fishing – trapping – and vermin destroying

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437 47, 437 60, 148DIG14, 148DIG109, H01L 2170

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active

051008289

ABSTRACT:
A method of manufacturing a semiconductor memory includes the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer simply except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulating film by etching one after another to form the contact hole extending to the diffused region in self-alignment.

REFERENCES:
patent: 3984822 (1976-10-01), Simko et al.
patent: 3986903 (1976-10-01), Watrous, Jr.
patent: 4268951 (1981-05-01), Elliott et al.
patent: 4327476 (1982-05-01), Iwai et al.
patent: 4577392 (1986-03-01), Peterson
patent: 4774206 (1988-09-01), Willer
patent: 4852062 (1989-07-01), Baker et al.
patent: 4879254 (1989-11-01), Tsuzuki et al.
patent: 4889827 (1989-12-01), Willer
patent: 4916083 (1990-04-01), Monkowski et al.
patent: 4951175 (1990-08-01), Kurosawa et al.
patent: 4965217 (1990-10-01), Desilets et al.
patent: 4977105 (1990-12-01), Okamoto et al.
patent: 5025741 (1991-06-01), Suwanai et al.
Patents Abstracts of Japan, vol. 14 No. 292 (E-944)(4235), Jun. 25, 1990; & JP-A-2 094 554 (Toshiba Corp.) 05-04-1990.
Patents Abstracts of Japan, vol. 11, No. 288 (E-542)(2735), Sep. 17, 1987; & JP-A-62 086 853 (Fijitsu Ltd.) 04-21-1987.

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