Process for manufacturing ultra-dense dynamic random access memo

Details Process for manufacturing ultra-dense dynamic random access memo Process for manufacturing ultra-dense dynamic random access memo

1991-05-03

1992-03-31

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437228, 437235, 437919, H01L 2170

Patent

active

051008262

ABSTRACT:
The process for creating multi-megabit DRAM memories comprises the following sequence of steps, which commence following an anisotropic etch of a first layer of type-1 insulative material (e.g. silicon dioxide), which creates wordline sidewall spacers: CVD deposition of a gap-filling layer of a type-2 insulative material (e.g. silicon nitride) having a high rate of etch selectively with respect to type-1 insulative material to a thickness sufficient to completely fill the gaps between wordlines; planarization of the gap-filling layer; removal of gap-filling insulative material in wordline gaps where bitline contact will be made; anisotropic removal of type-1 insulative material at the base of the bitline contact vias formed in the previous step; CVD deposition of a bitline polysilicon layer of sufficient thickness to completely fill the bitline contact vias; silicidation of the bitline polysilicon layer; deposition of a second layer of type-1 insulative material; patterning of the type-1 insulative-material-coated, silicided bitline polysilicon layer to form bitlines; blanket deposition of a third type-1 insulative layer; anisotropic etching of the third type-1 insulative layer in order to form bitline sidewall spacers; removal of gap-filling insulative material in storage-node plate contact regions; deposition of a storage-node polysilicon layer; and patterning of the storage-node poly layer.

REFERENCES:
patent: 4775550 (1988-10-01), Chu et al.
patent: 4879257 (1989-11-01), Patrick
patent: 4894351 (1990-01-01), Batty
patent: 4953126 (1990-08-01), Ema
Kimura et al., "A New Stocked Capacitor DRAM Cell Characterized by a Storage Capacitor on Bitline Structure" IEDM 88 pp. 596-599.

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