Method of making buried stacked transistor-capacitor

Details Method of making buried stacked transistor-capacitor Method of making buried stacked transistor-capacitor

1988-02-29

1992-03-31

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437 99, 437203, 437919, 357 236, H01L 2170

Patent

active

051008238

ABSTRACT:
A buried interconnected transistor and capacitor are formed in a trench etched in a semiconductor wafer having a lightly doped surface layer. The trench extends through the surface layer into the substrate. A dielectric liner is provided in the trench and the trench partially refilled with polysilicon up to the surface layer. The dielectric liner is removed thereby exposing sidewalls of the surface layer in the trench. Further silicon is deposited which forms additional poly material on the poly plug, single crystal material on the exposed epi-sidewalls, and further poly above the single crystal material. A dielectric is formed over the deposited material and a gate electrode deposited over the single crystal portion on the sidewall. The poly plug serves as one plate of a buried trench capacitor and the single crystal material accommodates the channel of the series MOSFET connected to the poly plug capacitor plate.

REFERENCES:
patent: Re32090 (1986-03-01), Jaccodine et al.
patent: 4240195 (1980-12-01), Clemens et al.
patent: 4536947 (1985-08-01), Bohr et al.
patent: 4569701 (1986-02-01), Oh
patent: 4577395 (1986-03-01), Shibata
patent: 4630237 (1986-12-01), Miura et al.
patent: 4650544 (1987-03-01), Erb et al.
patent: 4651184 (1987-03-01), Malhi
patent: 4672410 (1987-06-01), Miura et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4683486 (1987-07-01), Chatterjee
patent: 4683643 (1987-08-01), Nakajima et al.
patent: 4686552 (1987-08-01), Teng et al.
patent: 4688063 (1987-08-01), Lu et al.
patent: 4713678 (1987-12-01), Womack et al.
patent: 4728623 (1988-03-01), Lu et al.
patent: 4734384 (1988-03-01), Tsuchiya
patent: 4791463 (1988-12-01), Malhi
patent: 4797373 (1989-01-01), Malhi et al.
patent: 4824793 (1989-04-01), Richardson et al.
Mohan Rao, "Epitaxial Layer Blocks Unwanted Charge in MOS RAMs," Electronics 6-30-81, pp. 103-105.
A. H. Shah, "A 4-Mbit DRAM with Trench-Transistor Cell", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 618-626.

Affiliated with

Also associated with

Rating

Method of making buried stacked transistor-capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making buried stacked transistor-capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making buried stacked transistor-capacitor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2258930