Patent
1996-06-04
1998-03-03
Chan, Eddie P.
G06F 1216
Patent
active
057245509
ABSTRACT:
A circuit for responding to a microprocessor-generated write of a write-protected area of memory by invalidating a cache line corresponding to a write address in a microprocessor's internal cache by using a microprocessor address pin as a snoop invalidate signal during snoop cycles. This allows write-protected areas of a main memory to be cached in the internal cache of the microprocessor. The circuit monitors a processor bus to determine if the address associated with a write cycle corresponds to the write-protected area of memory. If so, the circuit latches in the write address, gains control of the processor bus by asserting an address hold signal to float the address pins of the microprocessor, and generates a snoop cycle on the processor bus. The cache line of the microprocessor's internal cache corresponding to the snoop address is invalidated, thereby preserving coherency of the write-protected data.
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patent: 5325499 (1994-06-01), Kummer et al.
patent: 5408636 (1995-04-01), Santeler et al.
Pentium Processor User's Manual, vol. 1: Pentium Processor Data Book, Intel Corp., pp. 1-7 to 1-13, 3-13 to 3-25, 5-7 to 5-8, 5-28, 5-43, 6-34 to 6-44 (1994).
Chan Eddie P.
Compaq Computer Corporation
Ellis Kevin L.
LandOfFree
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