System including processor and cache memory and method of contro

Details System including processor and cache memory and method of contro System including processor and cache memory and method of contro

1995-06-06

1998-03-03

Robertson, David L.

G06F 1208

Patent

active

057245487

ABSTRACT:
A system comprising a cache memory connected to a processor and a main memory wherein the processor has a unit for outputting a discrimination signal that indicates whether the access to said cache memory is a sequential address data access or a non-sequential address data access, and the cache memory has a unit for changing the processing in a cache-miss state based on the output discrimination signal. In the case of the non-sequential address data access, unnecessary access to the main memory is suppressed to reduce the penalty in the cache-miss state and, hence, to improve the efficiency of the whole system by realizing a high-speed operation.

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