Packet switching system

Multiplex communications – Wide area network – Packet switching

Patent

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H04L 1256

Patent

active

054024170

ABSTRACT:
A packet switching system includes a plurality of incoming channels, through which packets arrive. The system has a circuit providing arrival time information for header information of respective packets. The arrival time information is then copied by a copying circuit. The copied information is accumulated in an arrival time information accumulating circuit in an order of the arrival time. On the other hand, the packet is accumulated by a packet accumulating circuit in an order of the arrival time. A control circuit is adapted to output the packets accumulated in the packet accumulating circuit and having the arrival time information consistent with the arrival time information accumulated at the leading end of the arrival time information accumulating circuit. The packets are output from the packet accumulating circuit according to destinations contained in the header information thereof through a plurality of outgoing channels for feeding out the routed packets.

REFERENCES:
patent: 4551833 (1985-11-01), Turner
patent: 4899335 (1990-02-01), Johnson, Jr. et al.
patent: 5274642 (1993-12-01), Widjaja et al.
Hayashi et al., "A Study On Control Algorithm For Large Scale ATM Switch", The Institute of Electronics, Information and Communication Engineers Technical Study Report, Switching System Engineering, SSE 89-173, (1989).

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