Method of manufacturing a novel static memory cell having a tunn

Details Method of manufacturing a novel static memory cell having a tunn Method of manufacturing a novel static memory cell having a tunn

1996-06-03

1997-09-30

Tsai, Jey

Fishing, trapping, and vermin destroying

437 40, 437 41, 437904, H01L 2170, H01L 2700

Patent

active

056725361

ABSTRACT:
A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.

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