Static information storage and retrieval – Floating gate – Particular biasing
Patent
1993-10-07
1995-03-28
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular biasing
365218, 257322, G11C 1140
Patent
active
054023718
ABSTRACT:
The present invention provides a method of writing data into and erasing it from a semiconductor nonvolatile memory having two diffusion layers formed in a semiconductor substrate, a floating gate formed on a layer between the two diffusion layers, a control gate and a select gate formed on a side portion of the control gate. The method is achieved by applying a potential enabling a channel to be formed between the two diffusion layers to the control gate, applying a potential preventing the channel from being formed therebetween to the select gate, injecting an electric charge into the floating gate without causing current to flow between the diffusion layers and writing data into the semiconductor nonvolatile memory. Thus, when such a method is used, the semiconductor nonvolatile memory can be operated with low energy and the number of times in which the data is reloaded or rewritten can be made greater.
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patent: 5168465 (1992-12-01), Harari
patent: 5235544 (1993-08-01), Caywood
patent: 5280446 (1994-01-01), Ma et al.
K. Naruke et al, "A New Flash-Erase EEPROM Cell With a Sidewall Select-Gate on its Source Side", IEDM, 1989, pp. 603-606.
Electronic Design, vol. 31, No. 17, Aug., 1993; pp. 189-196; "EEPROM Adapts Easily to In-System Changes", F. Jones et al.
OKI Electric Industry Co., Ltd.
Popek Joseph A.
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