Polysilicon gate reoxidation in a gas mixture of oxygen and nitr

Details Polysilicon gate reoxidation in a gas mixture of oxygen and nitr Polysilicon gate reoxidation in a gas mixture of oxygen and nitr

Filed on

1996-05-23

Date issued

1997-09-30

Examiner

Picardat, Kevin

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437 41, 437240, 437239, H01L 21316

Type

Patent

Status

active

Patent number

056725256

Description

ABSTRACT:
A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF.sub.3 gas and O.sub.2 gas at a temperature from about 900.degree. C. to about 1050.degree. C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 .ANG. to about 400 .ANG..

REFERENCES:
patent: 4748131 (1988-05-01), Zietlow
patent: 5108935 (1992-04-01), Rodden
patent: 5372951 (1994-12-01), Anjum et al.
patent: 5552332 (1996-09-01), Tsang et al.
patent: 5599726 (1997-02-01), Pan
Wolf, Stanley Silicon Processing For The VLSI Era, vol. 1, pp. 57-58 1986.

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