System and method for synthesizing logic circuits with timing co

Details System and method for synthesizing logic circuits with timing co System and method for synthesizing logic circuits with timing co

1991-12-02

1995-03-28

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, G06F 1560

Patent

active

054023572

ABSTRACT:
In a computer aided design system, a netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The automatic circuit layout synthesis process begins by assigning an initial capacitance value to each node. Next, a routing difficulty value is computed, this value comprises a sum of routing difficulty values associated with each of the nodes in the integrated circuit. Capacitance values for the integrated circuit are then adjusted so as to reduce the computed routing difficulty. Finally, the netlist and adjusted capacitance values are passed to a silicon compiler for automatic placement and routing of a circuit having capacitance values not exceeding the adjusted capacitance values.

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"Circuit Placement for Predictable Performance" by Hange et al., IEEE International Conf. on Computer Aided Design, ICCAD-87, pp. 88-91, 1987.
"Analytical Power/Timing Optimization Technique for Digital System" by Ruehli et al., IEEE 14th Design Automation Conf., 1977, pp. 142-146.
"Timing Analysis for nMOS VLSI" by N. P. Jouppi, IEEE 20th Design Automation Conf., 1983, pp. 411-418.
"Timing Influenced Layout Design" by Burstein et al., IEEE 22nd Design Automation Conf., 1985, pp. 124-130.

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