Semiconductor memory device having scan path for testing

Details Semiconductor memory device having scan path for testing Semiconductor memory device having scan path for testing

1996-02-28

1998-03-03

Chung, Phung

Excavating

371 211, 371 271, 371 2234, G11C 2900

Patent

active

057243670

ABSTRACT:
An address generator circuit (21A) includes a shift register (28) for storing therein address data (AD) to be outputted. A plurality of memory circuits which are equal in one of the numbers of bits of X and Y addresses for specifying rows or columns of memory cell arrays and different in the other number, apply data to scan paths so that less significant bits of the addresses having the same number of bits are stored in a position closer to an input terminal. An XOR gate (27A) in the address generator circuit (21A) generates write data (DI) for writing RAMs (31, 32) from data (X0, Y0) stored in predetermined registers of the shift register (28).

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