Superscalar processor with multiple register windows and specula

Details Superscalar processor with multiple register windows and specula Superscalar processor with multiple register windows and specula

1995-09-01

1999-04-20

Kim, Kenneth S.

395569, 395587, 39580023, G06F 938

Patent

active

058965289

ABSTRACT:
A superscaler processor capable of executing multiple instructions concurrently. The processor includes a program counter which identifies instructions for execution by multiple execution units. Further included is a register file made up of multiple register window pointer selects one of the multiple register windows. In response to the value of the current window pointer, a return prediction table provides a speculative program counter value, indicative of a return address of an instruction for a subroutine, corresponding to the selected register window. A watchpoint register stores the speculative program counter value. A fetch program counter, in response to the speculative program counter value, stores the instructions for execution after they have been identified by the program counter.

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