Error correction method and apparatus for disk drive emulator

Details Error correction method and apparatus for disk drive emulator Error correction method and apparatus for disk drive emulator

1994-10-21

1997-09-16

Teska, Kevin J.

Excavating

371 30, G06F 1110

Patent

active

056689764

ABSTRACT:
An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM.sub.0 -REM.sub.3. The check remainder bytes REM.sub.0 -REM.sub.3 are utilized to generates syndromes S.sub.1, S.sub.3 and a factor S.sub.B, the syndromes in turn being used to obtain either one or two error location positions (.alpha..sup.L1, .alpha..sup.L2). The mathematical calculation circuit (104) not only generates the syndromes S.sub.1, S.sub.3 and factor S.sub.B, as well as the error location positions (.alpha..sup.L1, .alpha..sup.L2), but also generates the addresses of the bit errors in the sector (L1-64 [complemented], L2-64[complemented].

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