System and method for power management in self-resetting CMOS ci

Details System and method for power management in self-resetting CMOS ci System and method for power management in self-resetting CMOS ci

1995-06-05

1998-03-03

Trans, Vincent N.

Boots, shoes, and leggings

326 83, 326 86, H03K 1902, H03K 19094

Patent

active

057242496

ABSTRACT:
A "no select state" is implemented with self-resetting CMOS logic circuitry so as to essentially disable the resetting function of this logic circuitry when the logic circuitry is in an idle state. As an example, within a multiplier circuit in a processor, the selection inputs to a multiplexor circuit are de-selected when there is no need for the multiplier circuitry.

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patent: 5326965 (1994-07-01), Inoue
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patent: 5337285 (1994-08-01), Ware et al.
patent: 5362989 (1994-11-01), Hennedy
patent: 5371709 (1994-12-01), Fisher et al.
patent: 5434519 (1995-07-01), Trinh et al.

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