System and method for testing self-timed memory arrays

Details System and method for testing self-timed memory arrays System and method for testing self-timed memory arrays

1996-12-11

1999-04-20

Chung, Phung M.

Excavating

371 211, G11C 2900

Patent

active

058963995

ABSTRACT:
The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths. A system and method of testing and burning in self-timed memory arrays includes a Static Evaluate circuit applied to the decoding function and the writing function of the array, a circuit for holding an address or write data inactive for the first part of a cycle, a circuit for activating the address or write data for the second part of a cycle, and a circuit for ensuring that the array resets correctly.

REFERENCES:
patent: 3961250 (1976-06-01), Snethen
patent: 5008569 (1991-04-01), Roy
patent: 5748012 (1998-05-01), Beakes

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