Semiconductor memory system using a clock-synchronous semiconduc

Details Semiconductor memory system using a clock-synchronous semiconduc Semiconductor memory system using a clock-synchronous semiconduc

1997-09-08

1999-04-20

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365194, G11C 800

Patent

active

058963472

ABSTRACT:
A semiconductor memory system using a synchronous memory and operating at a higher speed due to a reduced margin required when reading data from the SDRAM, and a semiconductor memory device for achieving the same are disclosed. The semiconductor memory system comprises at least one semiconductor memory device and a control device for performing data input/output to and from the semiconductor memory device, wherein the control device outputs data to be stored in the semiconductor memory device, synchronously with a first synchronizing signal that the control device outputs, and the semiconductor memory device delivers output data therefrom synchronously with a second synchronizing signal that the semiconductor memory device outputs. In the thus constructed semiconductor memory system, the semiconductor memory device incorporates an output phase shift circuit which introduces a prescribed phase angle between the output data and second synchronizing signal, and provisions are made so that at the semiconductor memory device side the output data and the second synchronizing signal are controlled precisely at the prescribed phase angle with respect to each other, and so that a latch pulse can be immediately generated at the controller side upon reception of a data strobe signal.

REFERENCES:
patent: 5371715 (1994-12-01), Kim
patent: 5479646 (1995-12-01), Proebsting
patent: 5627795 (1997-05-01), Nitta
patent: 5694371 (1997-12-01), Kawaguchi
patent: 5715198 (1998-02-01), Braceras et al.
patent: 5767715 (1998-06-01), Marquis et al.

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