Method of forming a bit line over capacitor array of memory cell

Fishing – trapping – and vermin destroying

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437919, 437977, H01L 2172

Patent

active

054016819

ABSTRACT:
A method of forming a bit line over capacitor array of memory cells includes, a) providing an array of word lines; b) providing active areas about the word lines to define an array of memory cell FETs; c) providing a layer of electrically insulating material over the word lines and active areas; d) providing first and second respective contact openings through the insulating material layer to capacitor and bit contact active regions; e) providing electrically conductive material within the first and second contact openings which electrically connects with the respective capacitor and bit active regions, with the electrically conductive material within the respective first and second contact openings collectively extending elevationally over and above the insulating material upper surface, the electrically conductive material within the first contact openings electrically connecting with the electrically conductive material of the second contact openings above the insulating material upper surface; and f) in a single step, chemical-mechanical polishing the collective electrically conductive material extending over and above the insulating material upper surface downwardly to at least the upper surface of the insulating material, the single chemical-mechanical polishing step effectively electrically isolating the conductive material within the first contact openings from the conductive material within the second contact openings.

REFERENCES:
patent: 5134086 (1992-07-01), Ahn
patent: 5227322 (1993-07-01), Ko et al.
patent: 5266514 (1993-11-01), Tuan et al.
Ahn, J. H., et al.: "Micro Villus Patterning (MVP) Technology for 256 Mb DRAM Stack Cell", 1992 Symp. on VLSI Tech. Dig. of Tech. Papers, pp. 12-13.

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