Boots – shoes – and leggings
Patent
1978-09-06
1981-03-31
Ruggiero, Joseph F.
Boots, shoes, and leggings
G06F 946
Patent
active
042597170
ABSTRACT:
An information processor is comprised of a plurality of circuits each of which is controlled by firmware and connected to a common bus and has a contention circuit for the bus. An arithmetic control unit for controlling the execution of the firmware is provided with a timing control circuit. When the arithmetic control unit is going to issue a bus use request or has issued the request of when it is issuing an interrupt inhibit instruction or interrupts its operation, another unit connecting to the common bus seizes the bus and interrupts the arithmetic control unit. In such a case, the timing control circuit causes the execution timing of the arithmetic control unit to be in a wait state and accepts the interrupt.
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patent: 4020472 (1977-04-01), Bennett et al.
patent: 4025906 (1977-05-01), Riikonen
patent: 4050097 (1977-09-01), Miu et al.
patent: 4080652 (1978-03-01), Cronshaw et al.
patent: 4086626 (1978-04-01), Chung
patent: 4086627 (1978-04-01), Bennett et al.
Ruggiero Joseph F.
Tokyo Shibaura Denki Kabushiki Kaisha
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